1. Field of the Invention
The present invention relates to semiconductor devices having a vertical channel MOS gate structure and more particularly to power devices having U-shaped and V-shaped grooves.
2. Description of the Background Art
A DMOSFET structure in which channels are formed laterally along a substrate surface is a dominant MOSFET structure for power devices. It has been indicated, however, that the structure finds difficulty in size reduction of unit cells and high integration for reduction in ON-voltage.
For solving the disadvantages, a MOSFET having U-shaped grooves or a trench structure has been proposed. FIG. 17 shows a conventional power MOSFET having a U-groove gate structure.
The power MOSFET of FIG. 17 comprises a drain electrode metal 7, a drain region 1, an N diffusion region 2 and a body 3 which are stacked in this order. Source regions 5 are formed in the surface of the body 3 by impurity diffusion. U-shaped grooves 40 are formed from the source regions 5 through the body 3 into the N diffusion region 2. Buried gate electrodes 4 are provided within the grooves 40 through gate oxide films 13. The source regions 5 and body 3 are covered with a source electrode metal 6, which is insulated from the buried gate electrodes 4 by oxide films 14. Such a U-groove gate structure is advantageous for reduction in ON-voltage because channels are formed on all side walls of the grooves 40 so that the length of the grooves 40 is fully effectively utilized. The grooves 40 adjacent to each other, when spaced more shortly for size reduction and high integration, make it difficult to expose the body 3 between the source regions 5 adjacent to each other. This is caused by restrictions in fabricating techniques such as pattern and superposing accuracies in photolithography which are required in arranging the grooves 40 centrally of the source regions 5. This restricts the reduction of the all dimension and high integration of cells. Then there is a limitation in reducing on resistance.
Structures for avoiding such problems have been proposed. FIG. 18 shows another conventional power MOSFET. The rectangular source regions 5 are equally spaced perpendicular to the U-shaped grooves 40. The source regions 5 and body 3 are short-circuited by the source electrode metal 6 on exposed surface of body 3 at this spacing. Such a structure permits channel regions to be formed in self-aligned fashion independent of the pattern of the U-shaped grooves 40. Positional relation between the source regions 5 and U-shaped grooves 40 need not be determined with very high accuracy, and a high pattern accuracy is unnecessary.
However, the structure of FIG. 18 has shorter total channel width than the structure of FIG. 17. One of the improvements thereagainst is to increase the width of the source regions 5 to decrease the area of the exposed surface of the body 3. This increases a distance from the center to the short-circuited edge of the source region and increases the resistance between the both ends of the distance in the body 3 under the corresponding source region. Then, the short-circuited efficiency is weakened at the point of the body 3 under the center of source region, so that it is difficult to suppress faulty operations of the MOSFET due to parasitic NPN transistors. There is another disadvantage in reducing on-resistance in both structure shown in FIGS. 17 and 18.
FIG. 19 shows a cross section of the structure in the vicinity of the U-shaped groove 40 and a profile of impurity concentration in XX' direction (in the direction of thickness). The structure of FIG. 19 is applied to both of the MOSFETs of FIGS. 17 and 18. Electrons flow from the source regions 5 through the channel region in the body 3 and N diffusion region 2 to the drain region 1 when the MOSFET is on. (It should be noted that current flows in the direction opposite to the electrons.) An ON-resistance is hence determined by a source resistance R.sub.S in the source regions 5, a channel resistance R.sub.C in the channels to be formed in the body 3 adjacent to the grooves 40, a resistance R.sub.N in the N diffusion region 2 and a drain resistance R.sub.D in the drain region 1.
The source resistance R.sub.S is determined by the distribution of the impurity concentration of the source regions 5. Since the source regions 5 are formed by impurity diffusion from the surface of the body 3 in the conventional structure, regions 5a with relatively high impurity concentration are formed only about the surface of the body 3. As shown in the profile of FIG. 19, the impurity concentration of the source regions 5 decreases toward the drain region 1. The source resistance R.sub.S increases toward the drain region 1. Therefore, it is difficult to reduce the ON-resistance on the whole.
The vertical channel MOS gate structure is essentially efficient for reducing ON-resistance. However, as mentioned above, the conventional devices with the vertical channel MOS gate structure have some difficulties in reducing size and so on, then the adaptation is not fully exhibited.